Traditionally, high temperature C4 (Controlled Collapse Chip Connection) bumps have been used to bond a chip to a substrate. Conventionally, the C4 bumps are made from leaded solder, as it has superior properties. For example, the lead is known to mitigate thermal coefficient (TCE) mismatch between the package and the substrate. Accordingly, stresses imposed during the cooling cycle are mitigated by the C4 bumps, thus preventing delaminations or other damage from occurring to the chip or the substrate.
However, lead-free requirements imposed by the European Union onto electronic components are forcing manufacturers to implement new ways to produce chip-to-substrate-joints. For example, manufactures have used solder interconnects consisting of copper as a replacement for leaded solder interconnents. More specifically, another type of lead free chip-to-substrate-connection is copper pillar technology. In such joints, a solder C4 bump is replaced with a copper pillar or copper pillars plated onto a chip's Under Bump Metallization (UBM). Such connection allows plating of long (80-100 μm), small diameter (30-60 μm) copper pillars. Also, such chip to package connections are favorable since they offer higher connection density, superior electrical conductivity and allows more uniform current distribution and heat dissipating performance, and hence potentially increased reliability.
However, copper has a high Young's modulus and a high thermal expansion. This being the case, copper is not an ideal candidate for mitigating thermal coefficient (TCE) mismatch between the chip and the substrate. Accordingly, stresses imposed during the cooling cycle cannot be effectively mitigated by the copper pillars, thus resulting in fractures or delaminations or other damage to the package.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.